The present invention relates to a semiconductor integrated circuit fabricated in a semiconductor device which generates a voltage higher than the power source potential or lower than the grounding potential.
In semiconductor devices, generally, circuits for generating higher voltage than the power source potential and circuits for generating lower voltage than the grounding potential are often incorporated into one device. For example, in a semiconductor memory circuit, it is necessary to supply a higher potential than the power source potential to the memory circuit as a data writing potential. On the other hand, in order to prevent abnormal phenomenon called latchup or decrease the floating junction capacity, substrate voltage generating circuit is often incorporated into the semiconductor integrated circuit, and a voltage lower than the grounding potential generated from the substrate potential generating circuit is supplied to the semiconductor substrate.
FIG. 13 shows a prior art semiconductor integrated circuit fabricated in a semiconductor device for generating a higher voltage than the power source potential for such purpose. It shows an example of a memory circuit. FIG. 14 is a timing chart showing the voltage waveforms of nodes A to E in FIG. 13.
The operation is described below according to FIGS. 13 and 14.
A clock signal generally known as RAS or chip enable signal is fed to an input terminal A. When the potential of the input terminal A becomes high level, MOS transistors Q21, Q23 are turned on by inverters i21, i23, while MOS transistor Q22 is turned off by an inverter i22. As a result, an output terminal B is connected to a power source potential Vcc through MOS transistor Q21 and diode d21. Ignoring the forward voltage drop of the diode d21, the potential of the output terminal B is lower than the power source potential Vcc by the threshold voltage (VTQI) of the MOS transistor Q21, that is, Vcc - VTQ1. This potential Vcc - VTQ1 is supplied to a memory cell 23 composed of a MOS transistor Q24 and a capacitor C22. At this time, for example, if the potential of a bit line BL is almost equal to the power source potential Vcc, data cannot be written stably into the capacitor C22.
In order to avoid such malfunction, the potential of the output terminal B is boosted to a higher potential than the power source potential Vcc by means of oscillation circuit 21 and charge pump circuit 22. The boosting operation is as follows. When the potential of the input terminal A becomes high level and the MOS transistor Q23 is turned on, the oscillation circuit 21 composed of inverters i24 to i26 and MOS transistor Q23 starts to oscillate, and an oscillation output varying between the power source potential Vcc and grounding potential 0V is obtained at an output node C. The potential of node D of the charge pump 22 is equal to the power source potential Vcc when the oscillation circuit 21 is stopped. Provided that, the forward voltage drop of the diode d23 is ignored. In this state, the oscillation circuit 21 starts oscillation, and when the power source potential Vcc at the node C is supplied to the node D through the capacitor C21 in the first oscillation period, the potential of the node D is ideally boosted to twice the power source potential Vcc, that is, 2Vcc. This potential 2Vcc is transmitted to the node E through diode D22, and the potential of the node E becomes 2Vcc, too. As a result, the potential of the output terminal B is also ideally boosted to 2Vcc - VTQ1. Thereafter the same operation is repeated in every oscillation period of the oscillation circuit 21, and the potential of the output terminal B is boosted to a potential higher than the power source potential Vcc. Actually, however, due to various leak currents in the semiconductor integrated circuit, the voltage after boosting is saturated at a certain value, and finally the potential of the output terminal B is held at a potential higher than the power source potential Vcc as shown in FIG. 14B. By supplying this boosted potential to the gate electrode of the MOS transistor Q24 of the memory cell 23, data can be written stably into the capacitor C22.
FIG. 15 shows a prior art semiconductor integrated circuit fabricated in a semiconductor device for generating a substrate voltage lower than the grounding potential. FIG. 16 is a timing chart showing the voltage waveforms of nodes X, Y, Z in FIG. 15.
The operation is described below by referring to FIG. 15 and FIG. 16.
Inverters j21 to j25 connected in a loop form compose a self-excited oscillation circuit, and an oscillation output varying between the power source potential Vcc and grounding potential 0V is obtained at the node X as shown in FIG. 16. A capacitor Ca21 and diodes D21, D22 compose a charge pump circuit.
Suppose the potential of the node Y is 0V. When the potential of the node X becomes the power source potential Vcc, the potential of the node Y is also going to become the power source potential Vcc through the capacitor Ca21. Since the diode D22 becomes conductive at this moment, the potential of the node Y remains at 0V, provided that the forward voltage drop of the diode D22 is ignored. At this time, the potential of the node Z, that is, the semiconductor substrate potential is also 0V. On the other hand, when the potential of the node X is changed from the power source potential Vcc to the grounding potential 0V, the diode D21 becomes conductive, thereby the potential of node X is made lower. As a result, the potential of the node Y is lowered to nearly -Vcc. At this time, the diode D22 is not conductive, and the potential of the node Y is nearly kept at -Vcc. Accordingly, through the diode D21, the potential of the node Z is stepped down from 0V to nearly -Vcc. Afterwards, the potential of the node X is gradually increased from near -Vcc toward 0V by the leak current flowing in the resistor r21. As the potential of the node X drops again to 0V in this process, the potential of the node Z is pulled down again to nearly Vcc by the same operation as mentioned above.
By repeating such operation, the potential of the node Z is maintained at an average potential VA lower than the grounding potential 0V. By supplying the potential VA to the semiconductor substrate as the substrate potential, it is possible to prevent latchup and decrease the junction capacity, thereby the stable operation and high speed operation of a semiconductor device can be achieved.
Thus, in the conventional semiconductor integrated circuit, it is attempted to stabilize the operation and realize the high speed operation, by generating a potential exceeding the power source potential or grounding potential, and supplying the potentials to specified nodes of the semiconductor integrated circuit.
Incidentally, the power source potential of a semiconductor integrated circuit is set within a range of about the standard power source potential (for example, 5V).+-.10%, and in addition to the standard power source potential, the maximum rated voltage (for example, 7V) is determined, and the operation is generally guaranteed when a power source potential within the maximum rated voltage is supplied. Practically, a supply voltage close to the maximum rated voltage may be applied when testing semiconductor integrated circuits fabricated in a semiconductor device, or a supply voltage close to the maximum rated voltage may be applied when using the semiconductor integrated circuit device in a special application. Moreover, due to some abnormal action, a supply voltage close to the maximum rated voltage may be applied to the semiconductor integrated circuit.
In the conventional semiconductor integrated circuit shown in FIG. 13 and FIG. 15, when a power source potential close to the maximum rated voltage (for example, 7V) exceeding the standard power source potential (for example, 5V) is supplied, the reliability of the semiconductor integrated circuit is lowered.
For example, in FIG. 13, while the standard power source potential (5V) is being supplied, the potential at the output terminal B is boosted to about 7V according to the action mentioned above, but when a excessive supply voltage close to the maximum rated voltage (7V) is applied, the potential at the output terminal B may be boosted nearly to 10 V by the same action. If such a high voltage is supplied to the gate electrode of the MOS transistor Q24, an intense electric field is applied to the PN junction, and the stability of the operation is sacrificed. Further when an intense electric field is applied to the gate oxide film, the gate oxide film may be broken.
A similar problem may also occur in FIG. 15. The reason is as follows. The pulse width of the oscillation output of the oscillation circuit composed of inverters j21 to j25 of FIG. 15 is determined by the sum of the delay time of the inverters j21 to j25. The delay time of each one of the inverters j21 to j25 depends on the amplitude of the power source potential, and the higher the power source potential, the faster the switching speed becomes, and thereby, the delay time becomes shorter. That is, the pulse width of the oscillation output is narrowed, and the oscillation frequency becomes higher. In response to such action, the potential of the node Z in FIG. 15 (that is, the substrate potential) becomes lower. In other words, when an excessive power source potential close to the maximum rated voltage is supplied, the voltage supplied from the substrate voltage generation circuit shown in FIG. 15 to the semiconductor substrate becomes even lower. Thus, when an excessive low voltage is supplied to the semiconductor substrate, an intense electric field is applied to the PN junction or gate oxide film of the MOS device in the semiconductor integrated circuit device, thereby the breakdown of the gate oxide film and other problems are induced.
The invention is to present a semiconductor integrated circuit for solving such conventional problems.
It is hence a first object of the invention to present a semiconductor integrated circuit incorporating a circuit for generating a higher voltage than a power source potential, in which if an excessive power source potential exceeding a standard power source potential is supplied from outside, the higher voltage is automatically restrained.
It is a second object of the invention to present a semiconductor integrated circuit incorporating a circuit for generating a lower voltage than a grounding potential, and supplying the lower voltage to a semiconductor substrate as the substrate voltage, in which if an excessive power source potential exceeding the standard power source potential is supplied from outside, the substrate voltage is automatically suppressed so as to prevent an excessively low voltage from being supplied to the semiconductor substrate.
It is a third object of the invention to present a semiconductor integrated circuit device incorporating a circuit for generating a higher voltage than the power source potential and a lower voltage than a grounding potential, in which if an excessive power source potential exceeding the standard power source potential is supplied from outside, the absolute value of the higher voltage or lower voltage is reduced.